Operational amplifiers develop an offset voltage V.sub.offset during their operation. This offset voltage is the voltage appearing between the inverting and the non-inverting input ports when the output is near zero. It is caused by substantially unavoidable internal component mismatches. Its effect is to introduce an error in the output signal voltage level. This problem is of particular significance for high performance amplifiers, which are characterized by high gain, high stability, low noise and wide band capability, because the offset voltage undergoes at least as great a gain as the signal and therefore increases in severity with increasing gain.
The general approach to dealing with the offset voltage has been to periodically reset the amplifier during a nulling phase by connecting the output to the inverting input. This type of arrangement is described, for example, in U.S. Pat. No. 4,306,196 issued Dec. 15, 1981 to Dwarakaneth et. al. and assigned to the assignee of the present application. However, this type of resetting has the disadvantage that if the output is returned to zero during nulling, it must thereafter be driven back to the appropriate signal level. This degrades the settling time of the amplifier, especially if it is driving a capacitive load or if significant clock leakage is present.
One approach to compensating for offset voltage with minimum degradation in performance is by the use of circuits such as are described in U.S. Pat. No. 3,801,919 issued Apr. 2, 1974 to Wilkes et al. and U.S. Pat. No. 4,255,715 issued Mar. 10, 1981 to Cooperman. These circuits involve filtering the dc (direct current) level of the output on a continuous basis and using that level as a reference for continuously adjusting the offset compensation at the inputs. Such filtering arrangements require relatively complex circuitry.